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Concepteur(-rice) – Services applicatifs et intégrations Poste permanent Le Réseau de transport de l’agglomération de Longueuil (RTL) assure la mobilité des...

RTL Design / Microarchitecture Engineer. Design and implement RTL (SystemVerilog/Verilog) for complex digital blocks. Drive performance, power, and area (PPA) optimizations at the RTL and microarchitecture level.

Requires 7+ years experience in FPGA design, RTL, and wireless protocols.

Key Responsibilities: • Create RTL designs for complex digital blocks • Drive optimizations in performance, power, and area • Collaborate on verification for high coverage • Participate in architecture discussions and design reviews • Engage in simulation and debugging processes Requireme

Requires 7+ years experience in FPGA design, RTL, and wireless protocols.

Votre mission inclura l'analyse de la performance et la mise en œuvre de stratégies adaptées pour répondre aux besoins opérationnels du RTL. Key Responsibilities: • Définir la feuille de route des solutions d’affaires • Assurer la performance et disponibilité des processus �

Seeking an RTL/FPGA Design Engineer with 15+ years experience.

Key Responsibilities: • Définir et piloter la vision d’évolution des solutions d'affaires • Superviser l'implantation et la mise à jour des solutions • Gérer les incidents et les changements en lien avec les solutions • Élaborer des tableaux de bord de performance

Seeking an RTL/FPGA Design Engineer with 15+ years experience.

Senior ASIC Design Engineer needed to translate system requirements into design specifications and develop RTL logic.

Must have skills in RTL synthesis, CDC analysis, and scripting languages. Seeking an experienced RTL/FPGA Design Engineer with 15+ years in ASIC design, Verilog/System Verilog, and familiarity with networking protocols.