English Un outil interactif pour recruter et rechercher un emploi !

Résultats de recherche

Vos résultats de recherche pour le mot clé rtl

Concepteur(-rice) – Services applicatifs et intégrations Poste permanent Le Réseau de transport de l’agglomération de Longueuil (RTL) assure la mobilité des...

2 juin 2026 par Réseau de transport de Longueuil
Longueuil, Québec, Canada

Familiarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows. Experience debugging RTL issues using simulation logs and waveform viewers.

4 septembre 2026 par YO IT Consulting
ca

Seeking an experienced RTL/FPGA Design Engineer with 15+ years in ASIC design, Verilog/System Verilog, and familiarity with networking protocols. Must have skills in RTL synthesis, CDC analysis, and scripting languages.

3 septembre 2026 par LanceSoft
Boucherville, Quebec, ca

Seeking a Senior ASIC Design Engineer for AI/HPC SOCs, focusing on RTL logic design and lab troubleshooting.

3 septembre 2026 par Semiconductor Technology Firm
Varennes, Quebec, ca

Seeking a Senior ASIC Design Engineer for AI/HPC SOCs, focusing on RTL logic design and lab troubleshooting.

3 septembre 2026 par Semiconductor Technology Firm
Boucherville, Quebec, ca

Seeking a Senior ASIC Design Engineer to work on AI/HPC SOCs, involving RTL logic design and lab troubleshooting.

3 septembre 2026 par Btadesignservices
Varennes, Quebec, ca

Familiarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows. Experience debugging RTL issues using simulation logs and waveform viewers.

30 août 2026 par YO IT Consulting
ca

Responsibilities include RTL design, debugging, and lab validation using SystemVerilog.

14 juillet 2026 par Ciena Corporation
Varennes, Quebec, ca

Seeking an RTL/FPGA Design Engineer with 15+ years experience.

14 juillet 2026 par LanceSoft, Inc.
Boucherville, Quebec, ca

Responsibilities include RTL design, debugging, and lab validation using SystemVerilog.

14 juillet 2026 par Ciena Corporation
Boucherville, Quebec, ca

Senior ASIC Design Engineer needed to translate system requirements into design specifications and develop RTL logic.

14 juillet 2026 par BTA Design Services Inc.
Varennes, Quebec, ca