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Elevate your career as a Design Verification Engineer with eInfochips in San Jose, CA. Key Responsibilities: • Manage and execute complete verification cycles for projects • Develop and integrate BFM/Drivers/Monitors into test benches • Conduct gate-level simulations and assertions coding •

This pivotal role at Blue Origin entails leading the Design for Manufacturing Mechanical approach in their TeraWave Operations. Key Responsibilities: • Own DFX strategies and guide programs from concept to production • Integrate DFX principles into all stages of product development • Direct ne

Elevate your career at AtkinsRéalis as a Data Architect, focusing on data governance and enterprise design. Key Responsibilities: • Lead the design of enterprise data models and schemas • Maintain metadata and dataset documentation • Coordinate development and validation across teams • Addr

Mentor and inspire a focused design team while fostering a culture of creativity, collaboration, and design excellence. Vice President of Product Design. The VP of Product Design will partner cross-functionally with Merchandising, Growth, Sourcing, Brand & Creative, and Executive Leadership to bring

Own the architecture and design of fuse controller and other DFT IPs for cutting-edge SoC designs. Deep expertise in DFT design, methodology, and implementation. We are now looking for a Senior ASIC Design Engineer - DFX!.

Rejoignez Made by Gather en tant qu'Ingénieur Principal en Design et contribuez à l'innovation des appareils de cuisine. Principales responsabilités: • Diriger la conception technique d'appareils de cuisine innovants • Assurer la conformité et la performance des produits • Collaborer avec

Fondée en 2003 par l’entrepreneur Shae Hong, Made by Gather rend le design et l’innovation haut de gamme accessibles grâce à ses marques d’articles de cuisine et de style de vie, notamment Beautiful by Drew® et bella®. Depuis plus de 20 ans, nous mettons sur le marché des produits au des

Background in high‑performance design, such as CPU, GPU, LPU, implementation and timing convergence – this is a plus. We are seeking a Senior Physical Design and Timing Engineer to work on high‑frequency and low‑power NVIDIA CPUs, GPUs, LPUs and SoCs at block, cluster, and full‑chip levels

Key Responsibilities: • Develop and verify complex networking IP for SoC integration • Conduct rigorous trade-off analyses on design performance • Collaborate with architecture and design teams for effective execution • Produce high-quality documentation for several project phases • Design

Key Responsibilities: • Mentor design team to foster innovation and creativity • Oversee the seasonal development of apparel lines • Transform market insights into effective design strategies • Collaborate with merchandising to align offerings with pricing goals • Ensure adherence to devel